1. Technical Field
The present disclosure relates to a delay-locked loop circuit and, more particularly, to a delay-locked loop circuit of a semiconductor device and a method of controlling the same.
2. Discussion of Related Art
A delay-locked loop (DLL) circuit is frequently used in semiconductor integrated circuits to generate an internal clock signal. In a conventional DLL the internal crock signal is generated by delaying a system crock signal or an external clock signal by a predetermined time. The DLL detects the phase difference between the internal crock signal and the external clock signal and controls a delay time by performing a shift operation to synchronize the internal clock signal and the external clock signal.
A conventional semiconductor memory device includes a plurality of memory cells for storing data. In a conventional semiconductor memory device such as dynamic random-access memory (DRAM), the internal clock signal generated by a DLL may be used as a timing signal for read and write operations of the DRAM. A write operation is performed to store data to the memory cells, and a read operation is performed to output the data stored in the memory cells. Generally, the write operation has an active mode and a write mode, and the read operation has an active mode and a read mode. In the active mode, the semiconductor memory device generates an active command signal to activate the memory cells in preparation for a following write mode or read mode. When operated in the read mode, the semiconductor memory device generates a read command signal and accesses activated memory cells to read the stored data therein.
In general, in semiconductor memory devices, the current drawn when the memory cells are activated in the active mode or accessed in the read mode is greater than the nominal current drawn. Therefore, when the memory cells are activated in the active mode or accessed in the read mode, an internal supply voltage may be lowered and the voltage supplied to the DLL may be changed. When the voltage supplied to the DLL is changed, the delay time applied to the external clock signal may be changed and the synchronization between the external clock signal and the internal clock signal may not be completed. When there is no synchronization between the external and the internal clock signals, the DLL performs a shift operation, controls the delay time, and compensates for the voltage drop. As a result, the external clock signal and the internal clock signal may be synchronized by the DLL.
In the operation of semiconductor memory devices, there may be a time period in which all or a part of a circuit is inactive. Accordingly, a need exists for a circuit capable of deactivating the DLL when its operation is not required.